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| ? semiconductor components industries, llc, 2011 january, 2011 ? rev. 1 1 publication order number: ncv8881/d ncv8881 1.5a automotive buck regulator with watchdog the ncv8881 consists of a buck switching regulator (smps) with a combination smps output undervoltage monitor and cpu watchdog circuit. in addition, two fixed ? voltage low dropout regulator outputs are provided, and share an ldo output voltage status output. once enabled, regulator operation continues until the watchdog signal is no longer present. the ncv8881 is intended for automotive, battery ? connected applications that must withstand a 40 v load dump. the switching regulator is capable of converting the typical 9 v to 19 v automotive input voltage range to outputs from 3.3 v to 8 v at a constant switching frequency, which can be resistor programmed or synchronized to an external clock signal. enable input threshold and hysteresis are programmable, with the enable input state replicated at an open drain ignition buffer output. the regulators are protected by current limiting, input overvoltage and overtemperature shutdown, as well as smps short circuit shutdown. features ? 1.5 a switching regulator (internal power switch) ? 100 ma, 5 v ldo output ? 40 ma, 8.5 v ldo output ? operating range 5 v to 19 v ? programmable smps frequency ? smps can be synchronized to an external clock ? programmable smps output voltage down to 0.8 v ? 2% reference voltage tolerance ? internal smps soft ? start ? voltage ? mode smps control ? smps cycle ? by ? cycle current limit and short ? circuit protection ? internal bootstrap diode ? logic level enable input ? enable input hysteresis programmable by external resistor divider ? enable input state is replicated at an open drain output ? cpu watchdog with resistor programmable delays ? watchdog reset output also indicates smps output out of regulation ? battery input withstands load dump to 40 v ? low standby current ? thermal shutdown (tsd) ? ncv prefix for automotive and other applications requiring site and change controls ? these are pb ? free devices applications ? audio ? infotainment ? safety ? vision systems ? instrumentation marking diagrams http://onsemi.com so ? 16w ep pw suffix case 751ag 1 16 ncv8881 awlyywwg 1 16 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 32 of this data sheet. ordering information 1 16 pin connections ignbuf wdi rdly resb en sync rosc gnd 5p0 ldomon 8p5 vin sw bst fb comp (top view)
ncv8881 http://onsemi.com 2 cin cz1 rfb2 cp3 rp2 rfb1 cs8p5 cout dfw cbst l1 cp1 rz1 rosc rdly battery r1 sync reset watchdog out en ignbuf sync rosc resb wdi rdly gnd 8p5 bst vin sw fb comp ldomon 5p0 to cpu from cpu 5.0v regulated smps output regulated 8.5v regulated enable r2 rigbuf cs5p0 c8p5 bead monitor ldo rmon rresb buffer ignition figure 1. typical application 5p0 16 resb 4 vin 13 ignbuf 1 cz1 rfb2 oscillator rp2 rfb1 8p5 14 rosc 7 temp sense 8.5v wdi 2 gnd 8 c8p5 regulator sw 12 bst 11 cout dfw switcher l1 error amp ref fb 10 comp 9 cp1 rz1 vin_ov short ckt monitor rdly 3 sync 6 watchdog timer rosc rdly 5v regulator undervoltage battery tsd logic power switch comparator pwm nopulse run monitor sw_uv oc s+8.5 out ncv8881 reset input s+5 buffered cs8p5 cin cbst cp3 cs5 bead cpu sync watchdog hysteresis ldomon 15 en 5 r2 enable r1 enable ignition buffer fault(h) rh qh rigbuf enable rmon monitor monitor ldo dbst1 dbst2 rresb /uvlo qib qrb qlm clamp figure 2. ncv8881 detailed block diagram ncv8881 http://onsemi.com 3 maximum ratings rating symbol value unit min/max voltage on wdi ? 0.3 to 7 v min/max voltage on rdly ? 0.3 to 7 v min/max voltage on resb ? 0.3 to 7 v min/max voltage on en ? 0.3 to 10 v max en current 10 ma min en current (with zero vin voltage) ? 10 ma min/max voltage on sync ? 0.3 to 7 v min/max voltage on rosc ? 0.3 to 7 v min/max voltage comp ? 0.3 to 7 v min/max voltage fb ? 0.3 to 7 v min voltage sw ? dc ? 20 ns ? 0.7 ? 3 v max voltage vin to sw 40 v max voltage vin 40 v min/max voltage bst ? 0.3 to 30 v min/max voltage bst to sw ? 0.3 to 15 v min/max voltage on 8p5 ? 0.3 to 9.5 v max 8p5 current 70 ma min/max voltage on ldomon ? 0.3 to 7 v min/max voltage on 5p0 ? 0.3 to 7 v min/max voltage ignbuf ? 0.3 to 7 v storage temperature range ? 55 to +150 c operating junction temperature range t j ? 40 to + 150 c esd withstand voltage human body model machine model charged device model v esd 2.0 200 >1.0 kv v kv moisture sensitivity msl level 1 peak reflow soldering temperature 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. thermal characteristics parameter board/mounting conditions typical value unit minimum pad (note 1) 1 sq. inch (note 2) junction ? to ? case top ( jt , jt ) 30 16 c/w junction ? to ? pin 1( jl1 , jl1 ) 70 65 c/w junction ? to ? board ( jb , jb ) (note 3) 15 17 c/w junction ? to ? ambient (r ja , ja ) 150 55 c/w specific notes on thermal characterization conditions: note: all boards are 0.062? thick fr4, 3? square, with varying amounts of copper heat spreader, in still air (free convection) c onditions. numerical values are derived from an axisymmetric finite ? element model where active die area, total die area, flag area, pad area, and board area are equated to the actual corresponding areas. 1. 1 oz. copper, 17.2 mm 2 spreader area (minimum exposed pad, not including traces which are assumed). 2. 1 oz. copper, 645 mm 2 (1 in 2 ) spreader area (includes exposed pad). 3. ?board? is defined as center of exposed pad soldered to board; this is the recommended number to be used for thermal calculat ions, as it best represents the primary heat flow path and is least sensitive to board and ambient properties. ncv8881 http://onsemi.com 4 pin function descriptions pin no. symbol description 1 ignbuf this open drain output is pulled low whenever the en signal is latched and a low level is recognized at the en input. 2 wdi cmos compatible watchdog pulse input from a cpu. to be valid, the time between falling edges of this signal must be less than the programmed watchdog delay. 3 rdly delay programming pin for por, boot and watchdog delays. connect a resistor between this pin and ground. 4 resb this is an open drain output for resetting a cpu. resb goes low if the wdi signal period is longer than the programmed watchdog delay, if vin is above or below operating voltage, if the smps output is out of regulation, or if the part is in thermal shutdown. 5 en logic compatible enable input. once a high is received at the en pin, the part enters a startup sequence. until expiration of the soft ? start timer, a low at the en pin will shut off the part. upon expiration of the soft ? start timer, a low at the en pin will shut the part off only if the smps output is out of regulation, or the signal at the wdi input is not valid. 6 sync logic compatible synchronization input. grounding this input allows a resistor between the rosc pin and ground to control the switching frequency. connecting this pin to an external clock synchronizes switching to the rising edge of the clock. 7 rosc oscillator frequency programming pin. connect an external resistor from this pin to gnd to set the switching frequency. leave this pin floating to operate at the default frequency of the internal oscillator. switching frequency is not controlled by this resistance if a clock is present at the sync pin, but the resistance remains in control of the modulator ramp amplitude. 8 gnd battery return, and ground reference for output voltages. 9 comp switching regulator error amplifier output for tailoring smps transient response with external compensation components. 10 fb feedback input pin to program switching regulator output voltage, and detect a low or shorted smps output condition. 11 bst bootstrap input provides drive voltage higher than vin to the smps n ? channel power switch for minimum switch r ds(on) and highest efficiency. for a typical application connect a 0.1 f ceramic capacitor from this pin to the sw pin, in close proximity to both pins. 12 sw switching node of the switching regulator. connect the smps output inductor and cathode of the smps freewheeling diode to this pin. 13 vin input voltage from battery. place an input filter capacitor in close proximity to this pin. 14 8p5 output of the internal 8.5 v linear regulator. this provides regulated gate drive voltage to the smps power switch. for a typical application connect a 4.7 f ceramic capacitor in series with 0.5 from this pin to ground. 15 ldomon this open drain output is pulled low if either the 5p0 or 8p5 output is out of regulation. 16 5p0 output of the internal 5 v linear regulator. for a typical application connect a 4.7 f ceramic capacitor in series with 0.5 from this pin to ground. exposed pad solder this to a low thermal impedance path for cooling. ncv8881 http://onsemi.com 5 general specifications electrical characteristics (v vin = 13.2 v, v en = 2.0 v, c in = 4.7 f unless specified otherwise) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit vin uvlo start voltage threshold v strt 5.0 5.6 6.0 v stop voltage threshold v stp 4.2 4.6 5.0 v vin uvlo hysteresis v inhyst 0.7 1.1 v vin overvoltage stop voltage threshold v ovstp 19 20 21 v restart voltage threshold v ovstt 18 19.2 v quiescent current vin quiescent current i qmax v fb = 1 v, t j = 25 c, v sw = 0 v 2 5 ma vin shutdown current i qsbmax v en = 0 v, t j = 25 c, v sw = 0 v 10 15 a enable (en pin) en logic high threshold v ensthh 1.6 v en logic low threshold v ensthl 1.2 v en input current i enswl v en = 1.2 v 35 42 55 a en input current i enswh v en = 1.6 v 0.8 1.4 3.0 a response to open input ncv8881 is disabled enable delay en high to ldo turn ? on 38 50 s clamp current v en = 5 v 5 20 a clamp voltage i en = 10 ma 9 10.5 12 v ignition buffer (ignbuf pin) ignbuf output leakage v en > 1.6 v 0 5 a ignbuf output voltage low v igblo v en < 1.2 v, sinking 0.5 ma 0.02 0.1 v thermal shutdown (tsd) thermal shutdown t tsd (note 4) 160 170 180 c thermal shutdown hysteresis (note 4) 35 c 4. guaranteed by design. ncv8881 http://onsemi.com 6 ldo regulators electrical characteristics (v vin = 13.2 v, v en = 2.0 v, c in = 4.7 f unless specified otherwise) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit 5p0 output output uv start threshold v 5uvstt percent of v o5p0 91 95 99 % output uv stop threshold v 5uvstp percent of v o5p0 89 93 97 % output uv hysteresis v 5vuvh percent of v o5p0 2 % output voltage range v o5p0 no load 4.8 5.0 5.2 v line regulation i out = 1 ma, 6 v < v in < 19 v 4 mv/v current limit 105 160 205 ma dropout voltage i 5p0 = 70 ma, v 5p0 = 2% 315 (note 6) 400 mv output load capacitance range c o output capacitance for stability (note 5) 3.9 100 f output load capacitance esr range esr co esr for stability (note 5) 0.2 5 power supply ripple rejection psrr v vin = 13.2 v + 0.5 v pp 100 hz sine ? wave, c 5p0 = 10 f (note 5) 60 db startup overshoot r 5p0load = 5 k ; c 5p0 = 10 f (note 5) 3 % 8p5 output output uv start threshold v 8uvstt percent of v o8p5 91 95 99 % output uv stop threshold v 8uvstp percent of v o8p5 89 93 97 % output uv hysteresis v 8vuvh percent of v o8p5 2 % output voltage range v o8p5 no load; 9 v < v in < 19 v 8.26 8.5 8.74 v line regulation i out = 1 ma, 9.5 v < v in < 19 v 7 mv/v current limit 44 68 85 ma dropout voltage i 8p5 = 20 ma, v 8p5 = 2% 165 (note 6) 300 mv output load capacitance range c o output capacitance for stability (note 5) 3.9 100 f output load capacitance esr range esr co esr for stability (note 5) 0.2 5 power supply ripple rejection psrr v vin = 13.2 v + 0.5 v pp 100 hz sine wave, c 8p5 = 10 f (note 5) 60 db startup overshoot r 8p5load = 10 k ; c 8p5 = 10 f (note 5) 3 % output clamp voltage v clp8p5 i 8p5 = 67 ma into the ncv8881 9 11 13 v ldomon output output leakage v 5p0 > v 5uvstt and v 8p5 > v 8uvstt 0.2 5 a output voltage low v rblo v 5p0 < v 5uvstp or v 8p5 < v 8uvstp , sinking 0.5 ma 0.03 0.1 v 5. guaranteed by design. 6. t j = 125 c ncv8881 http://onsemi.com 7 smps regulator electrical characteristics (v vin = 13.2 v, v en = 2.0 v, v bst = v sw + 8.2 v, c bst = 0.1 f, c in = 4.7 f unless specified otherwise) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit soft ? start soft ? start completion time t ss 3 5 7 ms voltage reference (fb pin) fb voltage (comp connected to fb) v fbr t j = 25 c ? 40 c t j 150 c 0.792 0.784 0.8 0.8 0.808 0.816 v fb pin monitor (smps output monitor) fb monitor high threshold v fbmonh v fb increasing; percent of v fbr 91 95 99 % fb monitor low threshold v fbmonl v fb decreasing; percent of v fbr 89 93 97 % fb monitor hysteresis v fbmony 10 20 mv fb low to resb output delay t fbldly 2.5 10 s error amplifier fb bias current i fbbias v fb = v fbr ? 0.1 0.1 a dc gain a v (note 7) 70 db gain ? bandwidth product gbw (note 7) 8 mhz slew rate comp rising v fb = v fbr ? 25 mv, c comp = 50 pf, i comp = ? 1 ma, v comp within ramp voltage levels. (note 7) 6 v/ s slew rate comp falling v fb = v fbr +25 mv, c comp = 50 pf, i comp = 1 ma, v comp within ramp voltage levels. (note 7) 6 v/ s comp source current i source v comp = 2.2 v v comp = 3.2 v 1.5 1.8 4 4 10 10 ma ma comp sink current i sink v comp = 2.2 v v comp = 1.1 v 1.3 0.6 3 1.6 10 10 ma ma ramp peak voltage 2.8 3.1 3.2 v ramp valley voltage 1.1 1.2 1.3 v ramp amplitude 1.6 1.9 2.0 v oscillator frequency f osc r rosc = open rosc = 36 k 154 337 170 186 429 khz maximum rosc controlled frequency f oscmax resistor from rosc to gnd 500 700 850 khz rosc pin voltage v rosc r rosc = open 0.970 1.02 1.080 v synchronization frequency range f syncmx (note 7) 160 600 khz synchronization delay t sncdly from rising sync edge 200 370 500 ns de ? synchronization delay t usncdly from last rising sync edge; rosc = open 6.6 7.8 10 s input current v sync = 5.0 v 5 10 a sync logic high threshold v sncthh 2 v sync logic low threshold v sncthl 0.8 v response to input held high reverts to internal oscillator (note 7) 7. guaranteed by design. ncv8881 http://onsemi.com 8 smps regulator electrical characteristics (v vin = 13.2 v, v en = 2.0 v, v bst = v sw + 8.2 v, c bst = 0.1 f, c in = 4.7 f unless specified otherwise) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol synchronization minimum high pulse width t pwhimin time v sync is above 2 v (note 7) 50 ns minimum low pulse width t pwlimin time v sync is below 0.8 v (note 7) 50 ns duty cycle limitations minimum off time t minoff sw falling to sw rising 50 120 200 ns minimum on time t minon sw rising to sw falling 100 330 550 ns current limit current limit 1.75 2.2 3 a current limit response time (note 7) from time of power switch turn ? on 200 ns short circuit detector fb pin threshold v fbsc % of v fbr 70 76 85 % soft ? start timer t sstimr from start of soft ? start, % of t ss (note 7) 100 250 % power switch on resistance r dson v bst = v sw + 6.0 v, t j = 25 c (note 7) 360 m sw risetime inductor current = 1 a, t j = 25 c (note 7) 30 ns sw falltime inductor current = 1 a, t j = 25 c (note 7) 30 ns 7. guaranteed by design. ncv8881 http://onsemi.com 9 watchdog electrical characteristics (v vin = 13.2 v, v en = 2 v, c in = 4.7 f unless specified otherwise) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit watchdog input (wdi pin) input high voltage 2.0 v input low voltage 0.8 v input current v wdi = 5.0 v 5 10 a threshold frequency f wdth to prevent resb low r dly = 10 k r dly = 20 k r dly = 30 k 20.85 10.42 6.95 hz rdly input output voltage r dly = 10 k 0.917 0.99 1.067 v output voltage r dly = 30 k 0.940 1.02 1.092 v resb output output voltage low v rblo v fb < v fbmonl , sinking 0.5 ma 0.03 0.1 v output leakage v fb > v fbmonh 0.4 5 a por delay time t por v fb > v fbmonh to resb high; r dly = 10 k r dly = 20 k (note 8) r dly = 30 k (note 8) r dly = open; r osc = 36 k (note 8) r dly = open; r osc = open 4.0 8 12 5 10 15 6.0 12 18 50 110 ms boot delay time t bd resb high to low; r dly = 10 k r dly = 20 k (note 8) r dly = 30 k (note 8) r dly = open; r osc = 36 k (note 8) r dly = open; r osc = open 40 80 120 50 100 150 60 120 180 500 1100 ms watchdog delay time t wd wdi low to resb low; r dly = 10 k r dly = 20 k (note 8) r dly = 30 k (note 8) r dly = open; r osc = 36 k (note 8) r dly = open; r osc = open 48 96 144 60 120 180 72 144 216 550 1300 ms 8. guaranteed by design. ncv8881 http://onsemi.com 10 fault responses inputs response to a single fault event full operation restored by: fault event en en latch 5p0 8p5 smps resb vin undervoltage l unlatch shutdown shutdown shutdown low vin > uvlo, en high vin undervoltage h unlatch shutdown shutdown shutdown low vin > uvlo vin overvoltage l stays latched shutdown shutdown shutdown low vin < ov threshold vin overvoltage h stays latched shutdown shutdown shutdown low vin < ov threshold thermal shutdown l stays latched shutdown shutdown shutdown low decrease temp thermal shutdown h stays latched shutdown shutdown shutdown low decrease temp 5p0 out of regulation l stays latched current limited stays on stays on no effect remove overload 5p0 out of regulation h stays latched current limited stays on stays on no effect remove overload 8p5 out of regulation l stays latched stays on current limited stays on no effect remove overload 8p5 out of regulation h stays latched stays on current limited stays on no effect remove overload smps out of regulation l unlatch shutdown shutdown shutdown low en high smps out of regulation h stays latched stays on stays on stays on low remove overload smps shorted to ground l unlatch shutdown shutdown shutdown low en high smps shorted to ground h unlatch stays on stays on latched off low en low, then high watchdog signal invalid l unlatch shutdown shutdown shutdown low en high watchdog signal invalid h stays latched stays on stays on stays on pulses low apply valid wdi ncv8881 http://onsemi.com 11 typical performance characteristics 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 3. supply current (en low) vs. temperature current ( a) 13.2 v supply 6.0 v supply 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ? 40 ? 20 0 20 40 60 80 100 120 140 160 13.2 v supply 6.0 v supply current (ma) temperature ( c) figure 4. supply current (en high) vs. temperature 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 delay ( s) temperature ( c) figure 5. en delay vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 9.0 9.5 10.0 10.5 11.0 11.5 12.0 ? 40 ? 20 0 20 40 60 80 100 120 140 160 voltage (v) temperature ( c) figure 6. en clamp voltage vs. temperature 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 voltage (v) temperature ( c) figure 7. v in uvlo start voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 temperature ( c) figure 8. v in uvlo stop voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 voltage (v) ncv8881 http://onsemi.com 12 typical performance characteristics 19.8 19.9 20.0 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 temperature ( c) figure 9. v in ov stop voltage vs. temperature voltage (v) ? 40 ? 20 0 20 40 60 80 100 120 140 160 18.8 18.9 19.0 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 temperature ( c) figure 10. v in ov restart voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 voltage (v) 790 792 794 796 798 800 802 804 806 808 810 temperature ( c) figure 11. reference voltage vs. temperature voltage (mv) ? 40 ? 20 0 20 40 60 80 100 120 140 160 4.990 4.992 4.994 4.996 4.998 5.000 5.0 10.0 15.0 20.0 voltage (v) figure 12. 5p0 output voltage vs. input voltage voltage (v) 175 177 179 181 183 185 187 189 temperature ( c) figure 13. 5p0 output current limit vs. temperature current (ma) ? 40 ? 20 0 20 40 60 80 100 120 140 160 150 200 250 300 350 ? 40 ? 20 0 20 40 60 80 100 120 140 160 voltage (mv) temperature ( c) figure 14. 5p0 dropout voltage limit vs. temperature ncv8881 http://onsemi.com 13 typical performance characteristics 8.470 8.475 8.480 8.485 8.490 8.495 8.500 9.0 12.0 15.0 18.0 frequency (khz) voltage (v) figure 15. 8p5 output voltage vs. input voltage 65.0 66.0 67.0 68.0 69.0 70.0 71.0 72.0 73.0 74.0 75.0 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 16. 8p5 output current limit vs. temperature current (ma) 60 80 100 120 140 160 180 200 voltage (mv) temperature ( c) figure 17. 8p5 dropout voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 temperature ( c) figure 18. 8p5 output clamp vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 voltage (v) 0.000 0.010 0.020 0.030 0.040 0.050 voltage (mv) temperature ( c) figure 19. ldomon low voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 0.10 0.12 0.14 0.16 0.18 0.20 current ( a) temperature ( c) figure 20. ldomon leakage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 ncv8881 http://onsemi.com 14 typical performance characteristics 0.00 0.01 0.02 0.03 0.04 0.05 voltage (v) temperature ( c) figure 21. resb low voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 22. resb leakage vs. temperature 0.00 ? 0.05 ? 0.10 ? 0.15 ? 0.20 ? 0.25 ? 0.30 ? 0.35 ? 0.40 current ( a) 1.010 1.015 1.020 1.025 1.030 1.035 1.040 1.045 1.050 voltage (v) temperature ( c) figure 23. rosc voltage vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 0.970 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 24. rdly voltage vs. temperature 160 162 164 166 168 170 172 174 176 178 180 frequency (khz) temperature ( c) figure 25. switching frequency vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 rosc open 350 355 360 365 370 375 380 385 390 395 400 voltage (v) frequency (khz) temperature ( c) figure 26. switching frequency vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 rosc = 36 k ncv8881 http://onsemi.com 15 typical performance characteristics 650 660 670 680 690 700 710 720 730 740 750 temperature ( c) figure 27. maximum switching frequency vs. temperature frequency (khz) ? 40 ? 20 0 20 40 60 80 100 120 140 160 rosc = 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 28. smps current limit vs. temperature current (a) 75.0 76.0 77.0 78.0 79.0 80.0 temperature ( c) figure 29. smps short ? circuit threshold vs. temperature voltage (% of v ref ) ? 40 ? 20 0 20 40 60 80 100 120 140 160 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 temperature ( c) figure 30. smps ramp amplitude vs. temperature voltage (v) 3.0 3.5 4.0 4.5 5.0 current (ma) temperature ( c) figure 31. error amp source current vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 v comp = 2.2 v v comp = 3.2 v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ? 40 ? 20 0 20 40 60 80 100 120 140 160 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 32. error amp sink current vs. temperature current (ma) v comp = 2.2 v v comp = 1.1 v ncv8881 http://onsemi.com 16 typical performance characteristics 4.60 4.70 4.80 4.90 5.00 5.10 5.20 5.30 soft ? start time (ms) temperature ( c) figure 33. soft ? start time vs. temperature ? 40 ? 20 0 20 40 60 80 100 120 140 160 0.000 0.010 0.020 0.030 0.040 0.050 ? 40 ? 20 0 20 40 60 80 100 120 140 160 temperature ( c) figure 34. ignbuf low voltage vs. temperature voltage (v) 0 50 100 150 200 250 300 350 400 450 500 550 600 650 10 100 1000 switching frequency (khz) rosc resistance (k ) figure 35. switching frequency vs. rosc resistance 4 6 8 10 12 14 16 18 20 22 24 10 15 20 25 30 35 40 45 50 por delay (ms) r dly resistance (k ) figure 36. por delay vs. r dly resistance 50 75 100 125 150 175 200 225 250 275 300 10 15 20 25 30 35 40 45 50 watchdog delay (ms) r dly resistance (k ) figure 37. boot delay vs. r dly resistance figure 38. watchdog delay vs. r dly resistance 50 75 100 125 150 175 200 225 250 275 300 10 15 20 25 30 35 40 45 50 boot delay (ms) r dly resistance (k ) ncv8881 http://onsemi.com 17 typical performance characteristics 0 50 100 150 200 250 300 350 0 102030405060708090100 dropout voltage (mv) load current (k ) figure 39. 5p0 dropout voltage vs. load current 0 50 100 150 200 250 0 5 10 15 20 25 30 35 40 dropout voltage (mv) load current (k ) figure 40. 8p5 dropout voltage vs. load current t j = 25 c t j = 25 c ncv8881 http://onsemi.com 18 operating description input voltage vin is the power supply input for all ncv8881 functions. prior to the appearance of a valid high at the enable input (en pin), vin voltage above the v strt threshold produces a low level at the reset output (resb). input undervoltage shutdown an undervoltage lockout (uvlo) circuit monitors the voltage at the vin pin. if the voltage is below the v stp threshold it pulls resb low, inhibits switching, and shuts down the ldos. input overvoltage shutdown if input voltage is above the v ovstp threshold, resb is pulled low, switching is inhibited, the soft ? start circuit is reset, and the ldos are shut off. upon dropping below the v ovstt threshold, the ldos will powerup and the smps will begin a soft ? start sequence regardless of the state of the en signal. state diagram figure 41 shows the state diagram for the ncv8881. states within numbered ellipses have common responses (such as to input overvoltage and high temperature shutdown) which force an exit from all states within. ncv8881 http://onsemi.com 19 resb low ldos, smps off ldomon off por delay ldos, smps on resb low boot delay ldos, smps on resb high resb high ldos, smps on enable = 1 vin < 19v & temp ncv8881 http://onsemi.com 21 rhyst 30k r2 rpdown 1meg r1 threshold signal enable resistors external ncv8881 pin en comparator clamp figure 44. enable input hysteresis mechanism when the en pin is below v ensthl , rhyst is in parallel with rpdown making the internal resistance from the en pin to ground lower than when the en pin is above v ensthh . this produces hysteresis in the enable function when there is resistance between the source of the enable signal and the en pin. a resistive divider from the enable signal source to the en pin ( figure 44 ) allows a wide range of activation/deactivation voltages. note that this divider is also used in conjunction with an internal zener clamp to keep the en pin voltage below the maximum voltage rating when battery is the enable signal. given the lowest voltage that must enable the part vih min , and the highest voltage that must disable the part vil max the divider resistor values are: r1 = 0.7874 * ( vil max ? 1.27)/(0.0005556 * 1/r2) [k ] [r2 in k ] r2 = 1800*(1.2283 * vil max ? vih min )/( vih min ? 86.823 * vil max + 108.7) [k ] minimum hysteresis is: 0.0415 * r1 [v] [r1 in k ] ncv8881 enable input vilmax programming range versus vihmin setting must be off 0 1 2 3 4 5 6 7 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vihmin setting (v) voltage (v) figure 45. enable input vilmax programming range versus vih min setting ncv8881 http://onsemi.com 22 ignition buffer the ignition buffer output ignbuf reports the en pin voltage level (high or low) detected by the en input circuitry when the en signal is latched. the ncv8881 will pull the ignbuf output low if the enable signal is low, and release the ignbuf output if the enable signal is high. the ignbuf output is an open drain device which requires an external pullup resistor to a logic supply. ignbuf is no longer controlled by en when en transitions low if the en signal is not latched. thermal shutdown a thermal shutdown circuit will inhibit switching, reset the soft ? start circuit, and power down the 5p0 and 8p5 outputs if internal die temperature exceeds a safe level. operation is automatically restored when die temperature has dropped below the thermal restart threshold regardless of the state of the en signal. 5p0 output current limit 5p0 output current is limited above the specified output current capability in order to limit inrush current at turn ? on and also minimize power dissipation in the event of an output short circuit. output undervoltage monitor either the 5p0 output voltage must exceed v 5uvstt or the 8p5 output voltage must exceed v 8uvstt before the smps will begin soft ? start. if the output is below v 5uvstp , the ldomon output will be pulled low. stability considerations the output capacitor helps determine three main performance characteristics of a linear regulator: starting delay, load transient response, and loop stability. the optimum capacitor type and value will depend on these three characteristics, as well as cost, availability, size and temperature constraints. tantalum, aluminum electrolytic, film, and ceramic are all acceptable capacitor types for most applications. values of 1 f or more work in many cases, however attention must be paid to the equivalent series resistance (esr). aluminum electrolytic capacitors are the least expensive solution but both the value and esr of this type of capacitor change considerably at low temperatures ( ? 25 c or ? 40 c). the capacitor manufacturer?s data sheet must be consulted for this information. stability under all load and temperature conditions is guaranteed by a capacitor value greater than or equal to 4.7 f and esr between 0.2 and 5 . besides powering external loads, the 5p0 output can be used to provide a regulated voltage to an rosc pullup resistor as a convenient way to decrease the factory ? set switching frequency. 8p5 output the regulated voltage provided by the 8p5 output is used to power the internal gate drive circuitry, but can also provide current to modest external circuit loads that can tolerate significant spike noise at the smps switching frequency. current limit 8p5 output current is limited above the specified output current capability in order to limit inrush current at turn ? on and also minimize power dissipation in the event of an output short circuit. output undervoltage monitor either the 8p5 output voltage must exceed v 8uvstt or the 5p0 output voltage must exceed v 5uvstt before the smps will begin soft ? start. the ldomon output will be pulled low if the 8p5 output voltage is below v 8uvstp . output overvoltage clamp if current is forced into the 8p5 output, a clamp will limit the voltage in order to protect the gate driver circuit from excessive voltage. stability considerations the output capacitor helps determine three main performance characteristics of a linear regulator: starting delay, load transient response, and loop stability. the optimum capacitor type and value will depend on these three characteristics, as well as cost, availability, size and temperature constraints. tantalum, aluminum electrolytic, film, and ceramic are all acceptable capacitor types for most applications. values of 1 f or more work in many cases, however attention must be paid to the equivalent series resistance (esr). aluminum electrolytic capacitors are the least expensive solution but both the value and esr of this type of capacitor change considerably at low temperatures ( ? 25 c or ? 40 c). the capacitor manufacturer?s data sheet must be consulted for this information. stability under all load and temperature conditions is guaranteed by a capacitor value greater than or equal to 4.7 f and esr between 0.2 and 5 . smps operation ldo output undervoltage monitor besides requiring the input voltage to be above v strt and the en input to be above v ensthh , either the 5p0 output voltage must exceed v 5uvstt or the 8p5 output voltage must exceed v 8uvstt before the smps will begin soft ? start. soft ? start upon being enabled and released from all fault conditions, and after one of the ldo outputs reaches ncv8881 http://onsemi.com 23 regulation, a soft ? start circuit slowly raises the switching regulator error amplifier reference to v fbr in order to avoid overloading the input supply. voltage reference an internal, temperature compensated bandgap voltage reference provides the smps error amplifier and the 5p0 and 8p5 linear regulators with a stable, precision reference voltage. smps error amplifier the error amplifier is an operational amplifier. the voltage mode control method employed by the ncv8881 requires type iii compensation for optimum regulator response to load and line transients. the output voltage of the error amplifier controls the duty cycle of the power switch by controlling the moment at which the power switch shuts off (power switch turn ? ons occur at a fixed rate). smps oscillator with no connections to the rosc or sync pins, the ncv8881 switching frequency will be the factory ? set default frequency f osc of the internal oscillator. rosc smps frequency control connection of a resistor between the rosc pin and ground will raise the switching frequency above the factory ? set default according to the following equation. f sw 6840 r rosc ? 0.97 170 connection of a resistor between the rosc pin and 5p0 will lower the switching frequency below the default. the programmed switching frequency should be no higher than the highest synchronization frequency if synchronization is used. smps synchronization applying a clock signal to the sync pin will cause power switch turn ? on edges to coincide with rising edges of the applied clock signal. when synchronization will be significantly higher than the default frequency, an rosc resistor which sets the internal oscillator frequency at (but no higher than) the synchronization frequency can be used to maintain the switching frequency approximately the same as the synchronization frequency in the absence of the sync signal. besides controlling the switching frequency, the rosc resistor controls the internal ramp slope, and can be used to adjust the gain of the pulse width modulator. a steady low or high sync input will restore smps operation to the factory ? set default or rosc programmed frequency after the de ? synchronization delay. output voltage regulation monitor when the fb voltage is below v fbmonl , resb is pulled low, and the por, boot and watchdog delays are initialized. when fb voltage exceeds v fbmonh the por delay begins to time out. if, when the fb voltage is below v fbmonl , the soft ? start timer has expired and the en input is low, the ncv8881 will completely shut off (see figures 46 through 48). 0 8p5 1 234567 91011 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold current is limited regulation threshold figure 46. smps overload during startup ncv8881 http://onsemi.com 24 0 8p5 1 2 3 4 5 6 7 9 10 11 12 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold current is limited regulation threshold figure 47. smps overload after successful startup #1 smps overload after successful startup #2 0 8p5 1 234567 9101112 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold regulation threshold current is limited figure 48. smps overload after successful startup #2 smps current limit and short circuit protection every cycle, the power switch will be shut off if switch current exceeds the internal, fixed, current limit. after the soft ? start timer has expired , an extreme overload is prevented from producing switch current in excess of the current limit by detecting excessively low voltage at the fb pin and latching the smps regulator off. toggling the en input low then high, or cycling input voltage off and on is required to restart the smps (see bubble 5 of figure 41, and figures 49 ? 51). ncv8881 http://onsemi.com 25 0 8p5 1 2 3 4 5 6 7 9 10 11 12 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold current is limited smps latched off regulation threshold figure 49. smps short ? circuit during startup 0 8p5 1 2 3 4 5 6 7 9 10 11 12 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold current is limited smps latched off regulation threshold figure 50. smps short ? circuit after successful startup #1 ncv8881 http://onsemi.com 26 0 8p5 1 234567 9101112 output enable 5p0 vin 8 smps soft ? start timer short ? circuit threshold smps latched off regulation threshold figure 51. smps short ? circuit after successful startup #2 watchdog watchdog function the watchdog function monitors the wdi input to check that wdi pulses arrive more frequently than the programmed minimum rate. monitoring commences after two sequential time periods (the por and boot delays) which start when the smps output reaches regulation. after these initial time periods, time between wdi falling edges exceeding the watchdog delay indicates abnormal microcontroller activity, and the ncv8881 responds by pulling the open drain resb output low. a single external resistor from the rdly pin to ground programs the por, boot and watchdog delays. when enabled and upon the smps output reaching regulation, the ncv8881 enters the por delay period t por , during which the resb pin is held low. when the por delay expires, the ncv8881 enters the boot delay period t bd during which the resb output is allowed to be pulled up by the external resistance. when the boot delay expires, the watchdog circuit begins monitoring the wdi pin for a falling edge (from a microprocessor or other signal source). if a falling edge arrives before the watchdog delay period t wd expires, resb remains high and a new watchdog delay period is initiated. otherwise the ncv8881 enters another por delay period and the resb pin is pulled low, while the smps and ldo outputs continue to regulate. if en is low when the watchdog delay expires (no falling edge has occurred at the wdi input), resb is pulled low and the ncv8881 shuts off all power outputs (smps and ldos) and minimizes supply current. in order to ensure that wdi pulses keep resb from being pulled low, they must never occur further apart than the minimum specified t wd . however, resb is not guaranteed to be pulled low unless pulses occur further apart than the maximum specified t wd . removal of other conditions that cause resb to go low (v in > v ovstp , temperature > t tsd , and smps output voltage low) also initiate por and boot delays prior to resumption of wdi monitoring. figures 52 through 57 illustrate the action of resb and the por, boot, and watchdog delays during start ? up and shutdown. the watchdog delay is internally limited to a maximum value proportional to the switching period in case the resistance at the rdly pin becomes excessively high, such as would occur if the path from the rdly pin through the rdly resistance becomes an open circuit. ncv8881 http://onsemi.com 27 figure 52. watchdog never appears; en input high ? ; 0 wdi 1234567 9101112 resb e nable 3.3v watchdog delay delay vin 8131415 16 5v por boot delay watchdog delay delay por boot delay watchdog delay delay por boot delay delay por 0 watchdog stuck high, then recovers; enable = high wdi 1 234567 9101112 resb enable 3.3v wdi stuck high watchdog normal response delay vin 8 normal response 13 14 15 16 5v delay boot delay delay por boot delay delay por boot delay watchdog delay por figure 53. watchdog stuck high, then normal; en input high ncv8881 http://onsemi.com 28 0 watchdog stuck low , then recovers ; enable = high wdi 1234567 91011 resb enable 3.3v vin 8 wdi stuck low 5v normal response watchdog delay delay boot delay delay por boot delay d p watchdog delay por figure 54. watchdog stuck low, then normal; en input high 0 wdi 1234567 91011 resb enable 3.3v vin 8 wdi too slow 5v watchdog delay delay boot delay por del a po wdi too slow watchdog delay delay boot delay por figure 55. watchdog is too slow; en input high ncv8881 http://onsemi.com 29 watchdog stuck high; enable = low, then en = high restarts 3.3v wdi stuck high normal response 5v 0 wdi 1234567 9101112 resb enable vin 8 13 14 15 16 watchdog delay delay por boot delay delay por boot delay normal response figure 56. watchdog stuck high, en input low; then en goes high to restart the regulators 0 smps output out of regulation to resb low delay vfbmonl 1234567 9101112 resb 3.3v threshold 8 tfbldly 13 14 figure 57. resb pulled low as the smps output voltage (pullup source for resb) drops out of regulation application information input capacitors the primary input capacitor should be a ceramic of at least 4.7 f placed between the vin pin and the ground terminal of the smps freewheeling diode in order to reduce input voltage perturbations present when the ncv8881 smps is heavily loaded. a secondary 0.1 f ceramic capacitor positioned as closely as possible between the vin and gnd pins of the ncv8881 provides greater reduction of input perturbations than further increasing the value of the primary ceramic capacitor, and can be more effectively positioned than the larger 4.7 f capacitor without compromising pcb thermal conductivity. ldo output capacitor selection the ldos have been compensated to work with output capacitors above 3.3 f having an esr from 200 m up to 5 over the full range of output current and temperature. lower capacitance and esr can be used for lighter load requirements. tantalum, aluminum or polymer electrolytic, capacitors can be used. ceramic capacitors should have series resistance added to be within the recommended esr range. there are many capacitor vendors which supply automotive rated parts that fall within these ranges. for example, the suncon ep ? series aluminum electrolytic capacitors are well suited well for automotive radio applications. setting the smps output voltage to set the output voltage of the switching regulator, use the following equation: v swout v ref 1 r1 r2 (eq. 1) where v ref is the reference voltage, r1 is the resistor connected from v swout to the fb pin and r2 is the resistor connected from the fb pin to ground. to reduce the effect ncv8881 http://onsemi.com 30 of input offset current error, it is customary to calculate r1 with r2 set at 1 k . smps snubber a resistor and ceramic capacitor must be connected in series between the sw pin and ground. typical values are 10 and 1 nf. smps freewheeling diode selection the freewheeling diode in the smps provides the inductor current path when the power switch turns off, and is sometimes referred to as the commutation diode. the diode peak inverse voltage must exceed the maximum operating input voltage in order to accommodate any higher peak voltage produced by switchnode ringing. the peak conducting current is determined by the internal current limit. the average diode current can be calculated from the output current i out , the input voltage v in and the output voltage v swout by: i d(avg) i out 1 v swout v in (eq. 2) the freewheeling diode should have a current rating equal to the maximum ncv8881 current limit, such as the mbra340t3. inductor selection mechanical and electrical considerations, as well as cost influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in smps system, a minimum inductor value is particularly important in space ? constrained applications. from an electrical perspective, smaller inductor values correspond to faster transient response. the maximum current slew rate through the output inductor for a buck regulator is given by: inductor slew rate di l dt v l l (eq. 3) where i l is the inductor current, l is the output inductance, and v l is the voltage drop across the inductor. this equation indicates that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply sufficient charge to maintain regulation while the inductor current ?catches up? to the load. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. in continuous conduction mode, the peak ? to ? peak ripple current is calculated using the following equation: i pp t sw v swout l 1 v swout v in (eq. 4) where t sw is the switching period. from this equation it is clear that the ripple current increases as l decreases, emphasizing the trade ? off between dynamic response and ripple current. for most applications, the inductor value falls in the range between 10 h and 22 h. there are many magnetic component suppliers providing energy storage inductor product lines suitable such as the wurth tpc series or toko dsh104c series inductors, which are recommended for the automotive radio applications. smps output capacitor selection the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, it supplies the current to the load for first few microseconds, where after the controller recognizes the load transient and proceeds to increase the duty cycle. neglecting the effect of the esl, the output voltage has a first drop due to the esr of the capacitor. v swout(esr) i swout esr (eq. 5) a lower esr produces a lower v during load transient. in addition, a lower esr produces a lower output voltage ripple. the voltage drop due to the output capacitance discharge can be approximated using the following equation: v swout(charge) (eq. 6) i swout 2 l 2 c swout v in(min) d max v swout where, d max is the maximum duty cycle value, which is 90%. although the esr effect is not in phase with the discharging of the output voltage, v swout(esr) can be added to v swout(charge) to give a rough indication of the maximum v swout during a transient condition. simulation can also help determine the maximum v swout ; however, it will ultimately have to be verified with the actual load since the esl effect is dependent on layout and the actual load?s di/dt. smps input capacitor selection besides voltage rating, a primary consideration for selecting the input capacitor is input rms current rating. ncv8881 http://onsemi.com 31 i in(rms) d ( 1 d ) i swout ( 1 d ) 2 i swout 2 ( 1 d ) t sw v swout v f l 2 12 (eq. 7) where d is the duty cycle = t on /(t on +t off ), and v f is the forward voltage of the freewheeling diode. another consideration for the value of the input capacitor is the ability to supply enough input charge to satisfy sudden increases in output current (such as produced at start ? up, or upon maximum load step) without an unacceptable drop in input voltage. this is sometimes important when the input voltage initially rises past the undervoltage lockout threshold. smps compensation the ncv8855 utilizes voltage mode control. the control loop regulates v swout by monitoring it and controlling the power switch duty cycle. inherent with all voltage ? mode control loops is a compensation network. cout dfw vout switch ramp vref lout voltage error amp vin comp power esr c2 c3 c1 r3 r1 r2 dcr figure 58. the compensation network consists of the internal error amplifier and the impedance networks z in (r1, r3 and c3) and z fb (r2, c1 and c2). the compensation network has to provide a loop transfer function with the highest 0 db crossing frequency to have fast response and the highest gain in dc conditions to minimize the load regulation. the open-loop gain magnitude versus frequency plot of a stable control loop crosses zero db with close to ? 20 db/decade slope and a phase margin greater than 45 . ncv8881 http://onsemi.com 32 error amplifier closed loop gain compensation network modulator gain db out esr c esr = 1 out out lc c l = 1 2 2 1 1 c r z = () 3 3 1 2 1 c r r z + = ? ? ? ? ? ? ? ? + = 2 1 2 1 2 1 1 c c c c r p 3 3 2 1 c r p = figure 59. to reiterate, there are 3 primary goals to compensating. goal 1 is to have a high a unity gain bandwidth (ugb) that is greater than 1/10 the switching frequency f sw , but less than 1/2 the switching frequency. ugb is also known as the crossover frequency. this is the point where the loop gain = 0 db or a gain of 1. in the plot above, the ugb is the point where the red line crosses the tbd axis. goal 2 is to have the loop gain cross 0 db with a ? 20 db/decade slope also known as a ? 1 slope. goal 3 is to achieve over 45 of phase margin when the gain crosses 0 db. these are just goals. sometimes the crossover frequency is reduced below 1/10 f sw in order to meet goal 3. conversely, some designs will push the crossover frequency as high as it can (as long as it is below 1/2 f sw ) with a reduced phase margin of 30 in order to get a faster transient response. the only two absolutes are that the crossover frequency cannot exceed 1/2 f sw and the phase margin has to be greater than 0 at crossover. however, a smps operating towards these absolutes will experience severe ringing before it dampens out. to achieve the above goals, the following guidelines should be adopted. ? place z1 at half the resonance of lc ? place z2 at or around lc ? place p1 at esr ? place p2 at half the switching frequency performing these calculations will take some amount of iteration and bench testing is needed to verify results. on semiconductor has developed a tool to speed up the design process tremendously with great ease and accuracy. this tool can be downloaded by following the link below: http://www.onsemi.com/pub/collateral/compcalc.zip ordering information device package shipping ? NCV8881PWR2G soic ? 16w ep (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncv8881 http://onsemi.com 33 package dimensions soic ? 16 wide body exposed pad case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8881/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative |
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